IC697MDL252
在完成了Verilog 代碼設(shè)計后,我們進行了仿真、綜合驗證,前仿用Modelsim、綜合用Synplify Pro、 綜合后仿真用Cadence 中的NC_Verilog,主要由于NC_Verilog 在后仿中的速度要優(yōu)于Modelsim,提高了效 率;圖5 是用NC_Verilog 仿真設(shè)備的枚舉過程;
任何USB 的數(shù)據(jù)傳輸都是建立在成功通過枚舉的基礎(chǔ)上的,只有正確完成了枚舉,USB 主機和設(shè)備之 間的通信才正在建立起來。所以枚舉是USB 通信的最關(guān)鍵的一步。在驗證過程中模擬了PC 主機向設(shè)備發(fā)送 各種命令來完成枚舉。在圖5 中pid[3:0]中D、3、9、2、1、B 分別表示Setup、DATA0、IN、Ack、Out、 DATA1。當(dāng)設(shè)備插上PC 時主機會持續(xù)的SE0 來復(fù)位設(shè)備,這時設(shè)備的地址默認為00,然后主機第一次發(fā)送 Setup 包來獲取設(shè)備的前8 個設(shè)備描述符,當(dāng)設(shè)備成功返回數(shù)據(jù)后,主機第二次發(fā)送Setup 包來給設(shè)備配 置地址,從圖中faddr[7:0]可以看出我們給設(shè)備配置的地址為02,在這以后主機都是通過這個地址向設(shè)備 獲取全部的18 個設(shè)備描述符和全部的配置描述符集,在取完這些描述符后主機對設(shè)備進行配置,主機就識 別出設(shè)備了。
IC697MDL252聯(lián)系人:李先生
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IC697MDL252FISHER PROVOX CL7661X1-BA1 MPU/MEM CL7661X1-A5 MPU P2.2
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